Fast Algorithms for Static Compaction of Sequential Circuit Test Vectors

Two fast algorithms for static test sequence compaction are proposed for sequential circuits. The algorithms are based on the observation that test sequences traverse through a small set of states, and some states are frequently re-visited throughout the application of a test set. Subse-quences that start and end on the same states may be removed if necessary and suucient conditions are met for them. The techniques require only two fault simulation passes and are applied to test sequences generated by various test generators, resulting in signiicant compactions very quickly for circuits that have many revisited states. I Introduction Test sequence compaction produces test sequences of reduced lengths, which can greatly reduce the test application time. Test application time is important because it directly impacts the cost of testing. Two types of com-paction techniques exist: dynamic and static compaction. Dynamic test sequence compaction performs compaction concurrently with the test generation process and often requires modiication of the test generator. Static test sequence compaction is done in a post-processing step to test generation and is independent of the test generation algorithm and process. If dynamic compaction is used within the test generator, static compaction can further reduce the test set size after the test generation process is nished. Several static compaction approaches for sequential circuits have been proposed in the pastt1-3]. The static compaction techniques proposed in 1, 2] use overlapping and reordering of test sequences obtained from targeting individual faults to produce a minimal-length test set. Three static compaction techniques have been proposed by Pomeranz and Reddy 3] (which use multiple fault simulation passes), and they have shown that sub-sequences can often be removed from a test without reducing the original fault coverage. The three compaction techniques are based on vector insertion, omission, or selection. When a vector is to be omitted or swapped, the fault simulator is invoked to make sure the fault coverage is not aaected by the alteration in the test sequence. These techniques produce very compact test sets at the expense of long execution times; however, they may not be practical for very large circuits because of the large number of fault simulations required. Our approach to test compaction is based on the observation that test sequences traverse through a small set of states, and some states are frequently re-visited. Table 1 shows the number of vectors and states traversed by the HITEC 4, 5] test sets …